MD3880 features 2.5v 0.125v operation 4 independent channels fully differential inputs and outputs 0.74nv/hz input-referred noise at 18.5db gain ultra low current noise 0.35pa /hz 600k /17.5pf internal input impedance 100mhz ampli? er bandwidth linear-in-db continuous variable gain control four digital programmable gain settings for pga 60mhz whole channel bandwidth at maximum gain 70db maximum channel gain variable gain scaling control active input impedance matching applications medical ultrasound receiver lna & tgc doppler signal ampli? cation transducer signal conditioning ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the MD3880 is a 4-channel, variable gain ampli? er (vga) paired with a low noise ampli? er (lna) that delivers fully differential input and output for ultrasound applications. the 18.5db gain of the lna allows the whole channel to have 0.74nv/hz of input-referred voltage noise at 5mhz. the lna is capable of active impedance control to improve noise performance, provided that the applications can take advantage of input impedance matching. the output of the lna is fed directly into the vga without using an external coupling capacitor. the vga is composed of a voltage controlled attenuator (vca) and a programmable gain ampli? er (pga). the vca can be continuously varied linear-in-db by a control voltage (v tgc ) from 0db to a maximum 47db. in addition, the gain of the pga can be varied between four discrete settings. typical application circuit 4-channel low-noise ampli? er gnd v dd +2.5v c5 in 4 p in 4 n out 4 p out 4 n vca lna pga in 1 p in 1 n out 1 p out 1 n lna pga pa 1 p pa 1 n in 2 p in 2 n out 2 p out 2 n lna pga in 3 p in 3 n out 3 p out 3 n vca lna pga gsc tgc pg1 pg0 pdc ebc pa 2 p pa 2 n pa 3 p pa 3 n pa 4 p pa 4 n vca vca int. ref.
2 MD3880 ordering information device package option 84-lead bcc+ 7x7mm body, 0.80mm height (max.), 0.50mm pitch MD3880 MD3880b2-g -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v dd , positive supply -0.5v to +3.5v v in , any input pin voltage range -0.5v to v dd operating temperature -40c to +85c storage temperature -65c to +150c power dissipation 2.0w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. operating supply voltages (over operating conditions unless otherwise speci? ed, v dd = +2.5v, t a = 25c) sym parameter min typ max units conditions v dd power supply 2.375 2.5 2.625 v t a = -40c to +85c i ddq v dd supply current - - 45 ma power down, pdc=1, total of all channels i dd v dd supply current - 75 - ma pdc = 0 pwr power dissipation - 700 - mw total of all channels - 175 - mw per channel psrr psrr - -60 - db f = 100khz logic data and clock inputs characteristics (over operating conditions unless otherwise speci? ed, v dd = +2.5v, t a = 25c) sym parameter min typ max units conditions v ih input logic high voltage 0.8v dd -v dd v --- v il input logic low voltage 0 - 0.2v dd v --- i ih input logic high current - - 1.0 a --- i il input logic low current -1.0 - - a --- c in input logic pin capacitance - 10 - pf --- a44 b40 b32 a35 a22 b20 a13 b12 a12 b11 a1 b1 a23 b21 a34 b31 pin a1 mark 84-lead bcc+ (top view) product marking yyww MD3880b2 lllllllll l = lot number yy = year sealed ww = week sealed = green packaging pin con? guration 84-lead bcc+ package
3 MD3880 electrical characteristics (all typical values are under the condition of t a = + 25c, v dd = 2.5v, load resistance = 1k across the differential outputs, c load = 1pf, f in = 10mhz, pg0 = 0, pg1 = 0, v gsc = 2.5v, v cm = 1.25v, gain lna = 18.5db, single-ended input: r s = r in = 50. r in is formed by active termination with r fb = 237 and c fb , differential signal output, unless otherwise noted.) low noise ampli? er sym parameter min typ max units conditions g lna ampli? er gain - 18.5 - db --- r in input resistance - 600 - k without active termination c in input capacitance - 17.5 - pf without active termination i bias input bias current - 1 - na from esd leakage cmrr common mode rejection ratio - -65 - db pg0 = pg1 = v dd , v tgc = 2.0v, f = 1mhz v in input voltage range - 210 - mv ac-coupled v in-noise input voltage noise, 5mhz - 0.74 - nv/hz without active termination i in-noise input current noise - 0.35 - pa/hz without active termination nf noise ? gure - 2.3 - db f = 5mhz, without active termination - 3.7 - db r s = r in = 50, f = 5mhz with active termination bw bandwidth - 100 - mhz small signal bandwidth overall channel sym parameter min typ max units conditions gain w hole channel gain - 70 - db without active termination, max. gain bw vga -3db bandwidth - 60 - mhz small signal bandwidth at max. gain sr vga slew rate - 500 - v/s --- vo vga output signal range - 4 - v pp rl > 1k differentially r out output impedance - 3 - f = 5mhz, single ended i outs output short-circuit current - 40 - ma --- v in-noise input voltage noise - 0.8 - nv/hz at max. gain and 5mhz imd intermodulation distortion, two-tone - -76 - dbc 1mhz , v out = 1v pp , 30db gain - -70 - 10mhz , v out = 1v pp , 30db gain hd3 third harmonic distortion - -73 - dbc v out = 1v pp , 1mhz, 30db gain --69- v out = 1v pp , 10mhz, 30db gain - -55 - v out = 1v pp , 1mhz, 10db gain - -47 - v out = 1v pp , 10mhz, 10db gain hd2 second harmonic distortion - -87 - dbc v out = 1v pp , 1mhz, 30db gain - -70 - v out = 1v pp , 10mhz, 30db gain - -53 - v out = 1v pp , 1mhz, 10db gain - -51 - v out = 1v pp , 10mhz, 10db gain a out1db 1db compression point - -1.3 - dbm v out = 1v pp , f= 10mhz, 8db gain
4 MD3880 overall channel sym parameter min typ max units conditions cstk c rosstalk - -78 - db pg0 and pg1 = 1, 30db gain, 1mhz, 1v pp at adjacent channel t gd group delay variation - 2 - ns 2 mhz < f < 50 mhz, full gain range t olr overload recovery time - 5 - ns 8db gain, v in = 50mv pp to 1v pp change, f = 10mhz v dc-out dc output level, v in = 0 - 1.25 - v --- note: v in is the voltage at the non-inverting node of the amplifier. accuracy sym parameter min typ max units conditions g slope gain slope 31 33 35 db/v v gsc = 2.5v g mat ch. to ch. gain matching - 0.1 - db v tgc = 0v or 2.0v e gain gain error - 0.8 - db referenced to best ? t db-linear curve, 0.5v < v tgc < 1.7v v os-out output offset voltage - 20 - mv reference to 1.25v gain control interface sym parameter min typ max units conditions v tgc gain control voltage 0 - 2 v linear in db, see gain scaling diagram v gsc gain slope voltage 2.0 - 2.5 v about 41db/v at 2.0v and 33db/v at 2.5v r gsc input resistance of gsc - 120 - k --- r tgc input resistance of tgc - 1.5 - m connected to ? v gsc td tgc response time - 0.2 - s 95% full gain change pga gain control table pg1, pg0 pga gain (db) 0,0 35 0,1 40.5 1,0 46 1,1 51.5 tgc and gsc voltage for gain scaling 0 01.7 - 47 vca attenuation (db) tgc voltage (v) min. slope max. slope r s c c c fb r fb p a lna con? gurations for active feedback
5 MD3880 pin description pin name description v dd v dd voltage supply gnd ground avdd analog supply agnd analog ground in 1~4 p positive polarity lna input of channel 1~4 in 1~4 n negative polarity lna input of channel 1~4 pa 1~4 p channel 1~4 lna positive output pa 1~4 n channel 1~4 lna negative output out 1~4 p positive polarity pga output of channel 1~4 out 1~4 n negative polarity pga output of channel 1~4 pdc pdc = 1, power down and enable external biasing, 450k intermal pull down ebc external current biasing gsc input of gain scaling control for all channels a0, a1 reserved, should connect to av dd pg0, pg1 pga gain select inputs (pg0 = lsb, pg1 = msb) tgc attenuator control input cm0~4 0.1f bypass capacitors to ground pin # pin name pin # pin name pin # pin name pin # pin name a1 in 1 p a22 agnd a43 gnd b20 nc a2 in 1 n a23 av dd a44 agnd b21 out 4 p a3 pa 1 p a24 av dd b1 pa 1 n b22 cm4 a4 pa 2 n a25 agnd b2 av dd b23 out 4 n a5 av dd a26 out 3 p b3 agnd b24 av dd a6 pa 2 p a27 cm3 b4 in 2 p b25 av dd a7 pa 3 n a28 out 3 nb5 in 2 n b26 agnd a8 av dd a29 out 2 p b6 agnd b27 av dd a9 pa 3 p a30 cm2 b7 in 3 p b28 av dd a10 agnd a31 out 2 nb8 in 3 n b29 agnd a11 in 4 p a32 out 1 pb9 pa 4 n b30 cm1 a12 in 4 n a33 av dd b10 av dd b31 out 1 n a13 agnd a34 av dd b11 pa 4 p b32 nc a14 agnd a35 agnd b12 nc b33 nc a15 ebc a36 gnd b13 gnd b34 nc a16 agnd a37 v dd b14 pdc b35 nc a17 gsc a38 v dd b15 av dd b36 nc a18 cm0 a39 gnd b16 nc b37 nc a19 a0 a40 gnd b17 a1 b38 nc a20 pg1 a41 v dd b18 pg0 b39 nc a21 gnd a42 v dd b19 tgc b40 nc pin con? guration
6 MD3880 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-MD3880 nr051407 84-lead bcc+ package outline (b2) 7x7mm body, 0.80mm height (max.), 0.50mm pitch top view pin a1 mark side view bottom view d e a a2 a1 note 1 (index area e/2 x d/2) d2 e2 seating plane detail a a1 b1 9 x et 8 x et 11 x et 10 x et detail a er terminal tip et et/2 l1 l l b detail a a44 b40 symbol a a1 a2 b d d2 e e2 er et l l1 dimension (mm) min 0.65 0.05 0.60 0.20 6.85 4.55 6.85 4.55 0.50 bsc 0.50 bsc 0.20 0.10 ref nom - - 0.65 0.30 7.00 4.70 7.00 4.70 0.30 max 0.80 0.10 0.70 0.40 7.15 4.85 7.15 4.85 0.40 drawings not to scale. notes: details of pin 1 identi? er are optional, but must be located within the indicated area. the pin 1 identi? er may be either a m old, or an embedded metal or marked feature. 1.
|
